Thanks for building a pak file to flash our specific tablets, and furthermore, include Android 4.0 aka ICS.
In fact I'm very excited for several things:
- Of course, it's built with Android 4.0. (I haven't seen it yet, sorry)
- The power LED is still on when charging.
- Recovery menu works fine.
- You have root from start. (I haven't seen it yet, sorry)
- I haven't tested more because of... (continue reading)
I just flashed the firmware and in the third try I have finished the flashing without any errors.
Now, my issue is that, in the first boot (after wiping /data and /cache folders) the boot animation loops forever and I don't know how to fix it.
After that I reseted the tablet and then I entered in recovery menu: It works like a charm.
I just fixed the boot loop changing the file vortex_flash_fajue_core_128x8_512M.ini and it worked. The file is this:
[AddrInfo]
loadPlainTextAddr = 0x80e80000 // 最唗噩砉隴恅蚾婥華硊ㄛ珨啜岆0x80000000
loadCipherTextAddr = 0x80e80000 // 最唗噩砉躇恅蚾婥華硊
goAddr = 0x80e80000 // Power on霜最笢ㄛ蚾婥俇最唗噩砉綴ㄛ泐蛌堍俴腔華硊,珨啜扢离峈0﹝
[DfuAddrInfo]
loadPlainTextAddr = 0x80000000 // 最唗噩砉隴恅蚾婥華硊ㄛ珨啜岆0x80000000
loadCipherTextAddr = 0x80000000 // 最唗噩砉躇恅蚾婥華硊
goAddr = 0x0 // Power on霜最笢ㄛ蚾婥俇最唗噩砉綴ㄛ泐蛌堍俴腔華硊,珨啜扢离峈0﹝
[ImageInfo]
imageEncrypt = 0x0 // "最唗噩砉岆瘁衄樓躇0ㄩ拸樓躇ㄛimage最唗拸剒賤躇紱釬1ㄩ衄樓躇ㄛimage最唗剒猁酕賤躇"
imageNoCrcFlag = 0x1 // "岆瘁輛俴最唗噩砉腔CRC苺桄 0 - 輛俴最唗噩砉腔CRC苺桄ㄛ彆苺桄囮啖頗蛌善USB BOOT˙ 1 - 祥輛俴最唗噩砉腔CRC苺桄﹝"
imageDcacheEn = 0x1 // 岆瘁婓賤躇湖羲Dcache L1ㄛ祥湖羲L2, 0ㄩ祥湖羲dcache, 1ㄩ湖羲dcache
[imageStoreInfor]
imageStoreNum = 0x4 // 最唗噩砉湔揣腔爺杅
imageStoreCoreAddr[0] = 0x0 // "藩爺最唗噩砉湔揣腔block弇离勤衾Nandflashㄛ湔溫跡宒狟 [31:28] - 垀揭腔nand 郋晤瘍(植0羲宎) [27:0] - 蜆nand 郋奻醱block晤瘍(植0羲宎)勤衾SD/MMCㄛ湔溫跡宒狟 [31:0] - 湔溫勤茼腔block 晤瘍勤衾eMMCㄛ湔溫跡宒狟 [31:0] - 湔溫勤茼boot囀腔block 晤瘍"
imageStoreCoreAddr[1] = 0x0
imageStoreCoreAddr[2] = 0x0
imageStoreCoreAddr[3] = 0x0
imageStoreCoreAddr[4] = 0x0
imageStoreCoreAddr[5] = 0x0
imageStoreCoreAddr[6] = 0x0
imageStoreCoreAddr[7] = 0x0
[DDRCinfor]
ddramSize = 0x40000 // Board ddram 腔湮苤ㄛ眕KB 峈等弇
ddrcCfgWakeup = 0x17f0220 // ddrc cfg register, 蚳蚚衾wakeup 諷秶 // f 111(1) -Enable command queue reorder. 0 = disable 1 = enable
ddrcTrainingAddr = 0x200000 // ddrc training address
ddrcTrainingBypass = 0x1 // 岆瘁bypass ddrc 腔 trainingㄛ1-bypassㄛ0-enable
ddrcInitialDoneBypass = 0x0 // 岆瘁脤戙 ddrc configuration initial doneㄛ1-bypassㄛ0-enable
ddrNormalSelfRefByapss =0x0 //絞bypass == 1奀ㄛ瓏ormal sleep 爵腔refresh岆祥硒俴腔˙
ddrNormalSleepCfg1Bypass = 0x0 //絞 bypass == 1奀ㄛ佽隴cfg1 init ddr start 岆祥剒猁硒俴腔ㄛ瘁寀剒猁硒俴˙
ddrcSelfRefSomeCfg = 0x0 //豖堤赻芃陔羲宎ㄛDDRC2/3,LPDDRC 氝樓狟醱腔諷秶掀杻[29-26, 22,19]high -> low
ddrcZqCtrl0Bypass = 0x0 //婓data training 眳猁饜离ㄛLPDDR祥猁酕ㄛDDR2/3 詢奀斛剕酕,脹衾1奀祥硒俴˙
ddrcRegConfNum = 0x23 // 猁饜离腔ddrc 敵湔(婦嬤ddrc眈壽腔padc)杅醴
ddrcDllOffModeBypass = 0x1
// "猁饜离腔ddrc 敵湔華硊杅郪ㄛ妏蚚腴2弇酕晊奀諷秶[31:2]: 敵湔華硊[1:0]: 敵湔饜离晊奀陓洘 0: 祥剒猁晊奀 1: 璃晊奀100 cycle 2: 璃晊奀10000 cycle 3: 璃晊奀1000000 cycle"
ddrcRegAddr[0] = 0x60011000
ddrcRegVal[0] = 0x1770020
ddrcRegAddr[1] = 0x60011008
ddrcRegVal[1] = 0x542
ddrcRegAddr[2] = 0x60011010
ddrcRegVal[2] = 0x220
ddrcRegAddr[3] = 0x60011014
ddrcRegVal[3] = 0x0
ddrcRegAddr[4] = 0x60011018
ddrcRegVal[4] = 0xff
ddrcRegAddr[5] = 0x60011020
ddrcRegVal[5] = 0x115
ddrcRegAddr[6] = 0x60011024
ddrcRegVal[6] = 0x3011000
ddrcRegAddr[7] = 0x60011028
ddrcRegVal[7] = 0x55B600D
ddrcRegAddr[8] = 0x60011030
ddrcRegVal[8] = 0xA201145
ddrcRegAddr[9] = 0x60011034
ddrcRegVal[9] = 0xC2104050
ddrcRegAddr[10] = 0x60011038
ddrcRegVal[10] = 0xE568D6
ddrcRegAddr[11] = 0x60011040
ddrcRegVal[11] = 0x361004
ddrcRegAddr[12] = 0x60011044
ddrcRegVal[12] = 0x29000
ddrcRegAddr[13] = 0x60011050
ddrcRegVal[13] = 0x3b00000
ddrcRegAddr[14] = 0x60011054
ddrcRegVal[14] = 0x800000
ddrcRegAddr[15] = 0x60011058
ddrcRegVal[15] = 0x800000
ddrcRegAddr[16] = 0x60011064
ddrcRegVal[16] = 0xDD22EE11
ddrcRegAddr[17] = 0x60011068
ddrcRegVal[17] = 0x7788BB44
ddrcRegAddr[18] = 0x600110a8
ddrcRegVal[18] = 0x0
ddrcRegAddr[19] = 0x600110ac
ddrcRegVal[19] = 0x0
ddrcRegAddr[20] = 0x600110b0
ddrcRegVal[20] = 0x0
ddrcRegAddr[21] = 0x600110b4
ddrcRegVal[21] = 0x0
ddrcRegAddr[22] = 0x600110C8
ddrcRegVal[22] = 0x3333
ddrcRegAddr[23] = 0x60011080
ddrcRegVal[23] = 0x3707000
ddrcRegAddr[24] = 0x60011084
ddrcRegVal[24] = 0x0
ddrcRegAddr[25] = 0x60011088
ddrcRegVal[25] = 0x0
ddrcRegAddr[26] = 0x6001108C
ddrcRegVal[26] = 0x0
ddrcRegAddr[27] = 0x60011090
ddrcRegVal[27] = 0x0
ddrcRegAddr[28] = 0x60011094
ddrcRegVal[28] = 0x307000
ddrcRegAddr[29] = 0x600110A4
ddrcRegVal[29] = 0x0
ddrcRegAddr[30] = 0x60011110
ddrcRegVal[30] = 0xf0010700
ddrcRegAddr[31] = 0x60011114
ddrcRegVal[31] = 0x0
ddrcRegAddr[32] = 0x60011074
ddrcRegVal[32] = 0x2222
ddrcRegAddr[33] = 0x60011078
ddrcRegVal[33] = 0x00
ddrcRegAddr[34] = 0x60011004
ddrcRegVal[34] = 0x1
[NandflashInfor]
nandBlocksPerNand = 0x87 // 藩跺nandflash chip腔block 杅醴
nandPageSize = 0x88 // page湮苤(眕Byte峈等弇)ㄛ瞰512ㄛ2048ㄛ4096ㄛ8192脹
nandSpareSize = 0x89 // spare湮苤(眕Byte 峈等弇)ㄛ16ㄛ64ㄛ128ㄛ218脹
nandPagePerBlock = 0x90 // 藩跺block腔page杅醴
nandBbtLocation[0] = 0x91 // "暮翹bbt弇离ㄛ郔嗣峈4爺31:28 - 垀揭腔nand 郋晤瘍(植0羲宎)27:0 - 蜆nand 郋奻醱block晤瘍(植0羲宎)"
nandBbtLocation[1] = 0x92 // "暮翹bbt弇离ㄛ郔嗣峈4爺31:28 - 垀揭腔nand 郋晤瘍(植0羲宎)27:0 - 蜆nand 郋奻醱block晤瘍(植0羲宎)"
nandBbtNum = 0x95 // "悵隱腔bbt 爺杅 0: 羶衄bbtㄛload 最唗噩砉奀蔚祥統蕉BBT 準0: bbt腔湔溫爺杅ㄛload 最唗噩砉奀蔚統蕉BBT"
nandBbtPageNum = 0x51
nandEccType = 0x96 // "扢离最唗噩砉岆瘁妏蚚ECCㄛ眕摯妏蚚睡笱ECCㄗ蛁砩ㄩ掛統杅勤512Infor祥釬蚚ㄛ512infor婓page湮苤峈512B腔赽妏蚚ECC8ㄛ坳湮苤page腔赽苀珨妏蚚ECC16ㄘ0: 祥妏蚚ECC7: 4-bit ECC, ecc_length = 713: 8-bit ECC, ecc_length = 1326: 16-bit ECC, ecc_length = 2642: 24-bit ECC, ecc_length = 4256: 32-bit ECC, ecc_length = 5670: 40-bit ECC, ecc_length = 7084: 48-bit ECC, ecc_length = 84蛁砩ㄩ祥夔妏蚚奻醱扢离眳俋腔硉"
nandReadEdge = 0x97 // 饜离黍杅奀腔粒朓
nandDataWidth = 0x98 // 妏蚚腔nandflash 杅擂弇遵 0ㄩ8弇杅擂弇遵 1ㄩ16弇杅擂弇遵
nandReconfigBypass = 0x81 // // "岆瘁婓鳳善512 infor 綴笭陔饜离NFC0ㄩ岆腔ㄛ笭陔饜离1ㄩ祥蚚笭陔饜离"
[SDIOInfor]
sdSampleFallingEdge = 0x0 // 岆瘁婓sdclk 狟蔥朓粒摩杅擂
sdInternalDiv = 0x1 // 獗sdio 耀輸敵湔 CLK_CONTROL 鏡扴
sdReconfigBypass = 0x1 // SD/MMC 縐笢湔溫infor 腔華硊陓洘ㄛ嘐隅湔溫4爺infor, 藩爺infor蚕珨跺華硊悵湔
[CLKRSTInfor]
clkBypassCtrl = 0x001fe608
cpuClkCfg = 0x00031001 // CPU: 750MHz
cpuPllCfg = 0x02ed0019 // PLL1: 750MHz
busClkCfg = 0x04010162 // 333MHz
busPllCfg = 0x02990019 // PLL2: 666MHz
ddrcClkCfg = 0x00000102 // 333MHz
ddrcPllCfg = 0x02990019 // PLL2: 666MHz
storPeriSrcCfg = 0x02 // PLL3
//storPllCfg = 0x008f000C // PLL3: 288MHz
storPllCfg = 0x002F000C // PLL3: 96MHz
sdioMclkCfg = 0x03 // 24MHz
//sdioMclkCfg = 0x01 // 48MHz
//nfcClkCfg1 = 0x114
//nfcClkCfg2 = 0x115
//clkUartMclkCfg = 0x00000003 // UART working clock configuration register. 96 / 4 = 24MHz
clkUartMclkCfg = 0x0 // UART working clock configuration register. 48MHz
clkPerUartBcr = 0x002b001a // "Uart 疏杻薹饜离敵湔婓跦擂infor 綴ㄛuart耀輸腔奀笘褫夔頗蜊曹ㄛ籵徹掛敵湔笭陔饜离疏杻薹ㄛ妏眳睫磁115200"
//clkPeriMiscCfg = 0x00000005 // Miscellaneous Peripherals' working clock configuration register 288 / 6 = 48MHz
clkPeriMiscCfg = 0x00000001 // Miscellaneous Peripherals' working clock configuration register 96 / 2 = 48MHz
//clkPerTimerMclk = 0x1154 // timer 腔 MCLKㄛ等弇MHzㄛ饜离uart奀妏蚚
//clkMemMclkCfg = 0x1155 //饜离sram 睿 rom腔divider
//emiPllCfg = 0x1156 //饜离sram 睿 rom 腔pll
//clkConfDelay = 0x0
[EFUSEInfor]
efcPsReadWidth = 0x21 // "[3:0] efc_ps_width, efuse ps width[7:4] efc_read_width, read strobe pulse width"
efcStandbyWidth = 0x11 // standby stable timing
efcPgmWidth = 0xa6 // Typical program strobe pulse width
[USBInfor]
usbCBWReqCnt = 0x0
VenderCmdMode = 0x17 // "岆瘁豖堤USB vender command0-豖堤,狟婥俇image眕綴憩豖堤vender commandㄛ堍俴試試狟婥腔core image最唗1-祥豖堤,祥堍俴試試狟婥腔core image最唗ㄛ樟哿諉彶陔腔vender command2-祥豖堤USB筍岆堍俴試試狟婥腔core image最唗"
[PARTITION_SECTORS]
//Partition_System = 0x80000
//Partition_Data = 0x200000
//Partition_Cache = 0x80000
//Partition_Recovery = 0x40000
//Partition_Boot = 0x40000
Partition_System = 0x90000//256M
Partition_Data = 0x177000//750M
Partition_Cache = 0x20000//64M
Partition_Recovery = 0x10000//32M
Partition_Boot = 0x10000//32M
LABEL = VORTEX
I'm already testing the rom, greetings.
This post has been edited by BuhoSolitario: 26 April 2012 - 06:41 PM